Utilizing fine-pitch copper pillar bump technology with a spacing of up to 40 μm, this technology enhances Flip Chip packaging capability and complies with RoHS and green product standards. It is used in various advanced ICs and communication components.

Lead-free solder bumps (SnAg1.8) have become the mainstream, replacing traditional lead-based materials. They offer both environmental friendliness and high performance, and are used in Flip Chip packaging and WLCS modules, suitable for various advanced chip products such as memory, Wi-Fi, RF switches, power management ICs, and MEMS.

Wafer-Level Chip Scale Package (WLCSP) is an advanced technology in which the package size is the same as the chip itself, allowing direct attachment to the PCB. The electroplated-type WLCSP process is currently available, suitable for products such as DRAM, NOR Flash, FPGA, communication security chips, and power transistors.

The wafer thinning process grinds the wafer to an ultra-thin thickness, reducing package size and improving heat dissipation performance. Subsequently, back metallization is performed to form a conductive or heat-dissipating layer, enhancing the electrical performance and reliability of subsequent packaging and system integration.

Silicon photonics miniaturizes optical circuits onto a chip, enabling high-speed signal transmission through optical waveguides. It is applied in fields such as fiber-optic communications, optical LiDAR, quantum optics, and AI, complementing electronic computing.

Expose TSV tops from the wafer backside to enable metallization, redistribution, and electrical connection, supporting reliable bonding and functional integration in 2.5D / 3D semiconductor packaging.